-----------------------------------
-- CONTROLADOR DE DRAM				--
-- Creat per: Lluís Magí  2000	--
-----------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;    

ENTITY cdram IS
	PORT(
		clk			: in std_logic;     -- 16 MHz
		rd			: in std_logic;   -- a nivell baix
		wr			: in std_logic;	  -- a nivell baix
		ale			: in std_logic;
		fila		: in unsigned(9 downto 0);
		columna		: in unsigned(9 downto 0);

		data_user	: inout std_logic_vector(3 downto 0);
		data_ram	: inout std_logic_vector(3 downto 0);
		
		address		: out unsigned(9 downto 0);
		cas			: out std_logic;
		ras			: out std_logic;
		oe			: buffer std_logic;
		we			: buffer std_logic;
		f_cicle		: out std_logic
	);

	constant DELAY: integer := 2;
	constant TW: integer := 3;
	constant TRAD: integer := 4;
	constant TRCD : integer := 5;
	constant TR : integer := 6;
	constant TAR : integer := 7;
	constant TRAS : integer := 9;
	constant TRC : integer := 12;
	constant MAX : unsigned (9 downto 0) := "1111111111";

END cdram;

ARCHITECTURE arq_cdram OF cdram IS

	signal cont_row : unsigned(9 downto 0);
	signal r_busy, w_busy, busy : std_logic;
	signal c_trc_r: integer range 0 to TRC-DELAY;
	signal c_trc_rw: integer range 0 to TRC;
	signal rw_ras, r_ras : std_logic;
	signal dades : std_logic_vector(3 downto 0);
	signal espera : std_logic;

BEGIN

-------------- cicle de refresc ----------------------- 
--             TRC = Time Refresh Cicle 
	process(clk) 
	begin
		if rising_edge(clk) then
			if busy='1' then
				c_trc_r<=0;
			else
				if c_trc_r < TRC then
					c_trc_r<=c_trc_r+1;
				else
					c_trc_r<=0;
				end if;
			end if;
		end if;
	end process;


--    cicle de refresc : RETARD, RAS='0', RAS='1' ,...........
	process(clk)
	begin
		if rising_edge(clk) then
			if busy='0' then
				if c_trc_r < DELAY then
					r_ras<='1';
				elsif c_trc_r < TRAS then
					r_ras<='0';
				elsif c_trc_r<TRC then
					r_ras<='1';
				else
					r_ras<='1';
				end if;
			else
				r_ras<='1';
			end if;
		end if;
	end process;


---  contador de files pel refresc
	process(r_ras)
	begin
		if rising_edge(r_ras) then
			if busy='0' and espera='0' then
				if cont_row < MAX then
					cont_row <= cont_row + 1;
				else
					cont_row <= conv_unsigned(0,10);
				end if;
			end if;
		end if;
	end process;
			
-----------------  read and write ----------

--		Comptador de TRC pel Read i el Write 
	process(clk) 
	begin
		if rising_edge(clk) then
			if busy='1' then
				if c_trc_rw < TRC then
					if espera='0' then
						c_trc_rw <= c_trc_rw+1;
					end if;
				else
					c_trc_rw <= 0;
				end if;
			else
				c_trc_rw <= 0;
			end if;
		end if;
	end process;

--------  finalització del Write
	process(wr, espera)
	begin
		if espera='0' then
			w_busy <='0';
		elsif rising_edge(wr) then
			w_busy<='1';
		end if;
	end process;

----------  finalització del Read
	process(rd, espera)
	begin
		if espera='0' then
			r_busy <='0';
		elsif rising_edge(rd) then
			r_busy<='1';
		end if;
	end process;

-------   Inici del cicle de lectura/escriptura
	process(ale)
	begin
		if c_trc_rw = TRC or r_busy='1' or w_busy='1' then
			busy <= '0';
		elsif rising_edge(ale) then
			busy <= '1';
		end if;
	end process;

----  cicle de lectura/escriptura
	process(busy, c_trc_rw, clk)
	begin
		if busy='1' then
			if c_trc_rw < DELAY then        -- delay al inici
				rw_ras<='1';
				cas<='1';
				we<='1';
				oe<='1';
				espera<='0';
			elsif c_trc_rw < TRCD then     -- activació del RAS
				rw_ras <= '0';
				cas <= '1';
				we<='1';
				oe<='1';
				espera<='0';
			elsif c_trc_rw < TAR then       -- activació del CAS
				rw_ras<='0';
				cas<='0';
				we<='1';
				oe<='1';
				espera<='0';
			elsif c_trc_rw < TRAS then
				espera<='1';          -- esperem el senyal RD o WR
				rw_ras<='0';
				cas<='0';
				we <= wr;
				oe <= rd;
			else
				rw_ras <= '1';
				cas <= '1';
				we<='1';
				oe<='1';
			end if;
		else
			rw_ras<='1';
			cas<='1';
			we<='1';
			oe<='1';
			espera<='0';
		end if;
	end process;
				


---------------  actuació sobre la DRAM  -----------------
	ras <= r_ras and rw_ras;

-----------  adreçament --------------
	process(clk)
	begin
		if rising_edge(clk) then
			if busy='0' then
				address <= cont_row;
			elsif c_trc_rw < TW then
				address <= fila;
			else
				address <= columna;
			end if;
		end if;
	end process;

--  captura de la dada
	process(wr)
	begin
		if falling_edge(wr) then
			dades<=data_user;
		end if;
	end process;

-----  control de dades ...............
	process(clk)
	begin
		if oe ='0' then
			data_user <= data_ram;
		else
			data_user <= "ZZZZ";
		end if;
		if we='0' then
			data_ram<=dades;
		else
			data_ram<="ZZZZ";
		end if;
	end process;


---------------------------------------------------------------------------------------------

	process(rd)     -- control de l'inici del cicle de lectura
	begin
		if estat=3 then
			inici_r<='0';
		elsif falling_edge(rd) then
			inici_r<='1';
		end if;
	end process;

	process(wr)     -- control de l'inici del cicle d'escriptura
	begin
		if estat=3 then
			inici_w<='0';
		elsif falling_edge(wr) then
			inici_w<='1';
		end if;
	end process;

	process(clk)       -- control del cicle d'accés
	begin
		if rising_edge(clk) then
			case estat is
			when 0 =>
				if inici_r='1' or inici_w='1' then        --esperem inici
					estat<=1;
					address<=fila;
				end if;
				cas<='1';
				ras<='1';
				temps<=0;
			when 1 =>
				ras<='0';       -- activació del RAS
				cas<='1';
				if temps<TRCD then
					temps<=temps+1;
					estat<=1;
					if temps=TRAD then
						address<=columna;
					end if;
				else
					estat<=2;
				end if;
			when 2=>
				ras<='0';
				cas<='0';   -- activació del CAS
				if temps<TRAS then
					temps<=temps+1;
					estat<=2;
				else
					estat<=3;
				end if;
			when 3=>
				ras<='1';
				cas<='1';
				address<="ZZZZZZZZZZ";
				if temps<TRC then
					temps<=temps+1;
					estat<=3;
				else
					estat<=0;
				end if;
			end case;
		end if;
	end process;



end arq_cdram;