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On System-Level Verification of VLSI Signal Processing

Lan-Rong Dung and Tsung-Hsi Chiang

International Symposium on Performance Evaluation of Computer and Telecommunication Systems (SPECTS 2007)
San Diego, California (USA), July 16-18, 2007


Formal verification in high level design, which means architecture design, is different from functional verification in RTL level. DSP algorithms need high level transformation to achieve optimal goals before mapping on a silicon. However, there is absent of suitable CAD tool to support the simulation and verification in high level. This paper presents a novel modeling and formal verification methodology of dataflow graph in system level base on Petri net (PN) model. We present transformation from FSFG to PN model. Then, verification method which includes static and dynamic phase is also addressed. In the last, we introduced our software implementation, called HiVED, to show the experimental results.

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